1. Field of the Invention
Embodiments of the present invention relate to semiconductor devices.
2. Related Art
In conventional very large scale integration (VLSI) semiconductor devices, the n-wells and p-wells are formed in rows and columns that lie parallel to the horizontal and vertical axes. A voltage can be routed to, for example, the n-wells using interconnecting conductive paths (such as deep n-well). Because the n-wells are arrayed on a grid, the interconnecting conductive paths (such as deep n-well) are also typically arranged as a grid.
A problem with a grid or grid-like pattern of conductive paths is that the interconnects frequently coincide with the locations of p-wells, preventing the passage of leads (“vias”) that allow the p-wells to be connected to a substrate. That is, because both the p-wells and the interconnects lie in straight lines parallel to the horizontal and vertical axes, there can be many instances in which an interconnect lies under a row or column of p-wells.
One solution to the above problem is to rotate the grid-like pattern of interconnects so that they lie diagonally relative to the columns and rows of p-wells. However, while this solution can reduce the number of instances in which an interconnect lies under an entire row or column of p-wells, the X-shaped intersections of the interconnects still coincide frequently with locations of p-wells.
Another solution to the problems above is eliminate the X-shaped intersections by placing the interconnects along diagonals that run only in one direction (if the layout is viewed from above, then from the perspective of the viewer the interconnects run in parallel from, for example, the lower left to the upper right). However, this solution remains problematic because it sacrifices sheet resistance in the direction perpendicular to the diagonals. Furthermore, in instances where the n-wells are not large enough to bridge the distance between adjacent diagonals, a voltage will not be transported from one diagonal to the next.